The present invention pertains to dynamic random access memories (DRAMs) and more particularly to high density DRAMs. In the prior art, memory cells for DRAMs are constructed by forming trench capacitors in a substrate and using one or more planer transistors to connect the trench capacitors to an appropriate network of word and bit lines so as to form a memory. In these structures there are problems with "punchthrough" between adjacent cells, leakage, parasitic transistors, noise, alpha particles, etc. Also, because of the planar transistors the cell size is drastically limited and as attempts to reduce the size of the planar transistors are increased, the problems become greater.
Some efforts have been made to place at least one of the controlling transistors in the trench. However, this produces high resistance, high capacitance lines and connections to the transistors and capacitors, which results in increased signal-to-noise and substantially reduces the speed of the memory. Further, these DRAMs can be extremely complicated and expensive to manufacture.